Verification Methodology for DEVS Models

Modeling is an effective tool for studying the behaviour of a system. When modeling, the system’s descriptions are usually abstracted into simpler models. These models can then be analyzed and solved (manually or automatically) by using different mathematical techniques. However, sometimes the models become too complex to analyze formally. In those cases, computer Modeling and Simulation (M&S) can help designers to understand the behaviour of these systems better. One example of such complex systems are RealTime (RT) systems, which are usually composed of a digital computer executing software that interacts with the external physical environment with tight timing constraints. In studying these systems, M&S has proven to be an essential tool. However, when simulating RT models, the required interactions could quickly grow beyond the ability of human observation and analysis. Instead, formal methods for verifying these systems can guarantee the correct and timely function of these systems. Due to the benefits of formal verification of RT simulation models, this thesis introduces a methodology to enable performing formal verification o f simulation models based on the Discrete Event System Specification (DEVS) formalism. The thesis introduces a road map for a complete methodology to formally verify DEVS models, thus enabling better methods for M&S validation and verification and making M&S a better tool for RT-embedded systems development.